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CS3001 CS3002 Precision Low Voltage Amplifier; DC to 2 kHz
Features
Low Offset: 10 V Max Low Drift: 0.05 V/C Max Low Noise
- 6 nV/Hz @ 0.5 Hz - 0.1 to 10 Hz = 125 nVp-p - 1/f corner @ 0.08 Hz
Description
The CS3001 single amplifier and the CS3002 dual amplifier are designed for precision amplification of low level signals and are ideally suited to applications that require very high closed loop gains. These amplifiers achieve excellent offset stability, super high open loop gain, and low noise over time and temperature. The devices also exhibit excellent CMRR and PSRR. The common mode input range includes the negative supply rail. The amplifiers operate with any total supply voltage from 2.7 V to 6.7 V (1.35 V to 3.35 V).
Open-Loop Voltage Gain
- 1000 Trillion Typ - 10 Billion Min
Rail-to-Rail Output Swing 1.8 mA Supply Current Slew rate: 5 V/s
Pin Configurations
CS3001
PWDN -In 1 2 3 4 + 8 NC 7 V+ 6 Output 5 NC
CS3002
Out A 1 -In A 2 +In A 3 V- 4 A -+ B +8 V+ 7 Out B 6 -In B 5 +In B
Applications
Thermocouple/Thermopile Amplifiers Load Cell and Bridge Transducer Amplifiers Precision Instrumentation Battery-Powered Systems
+In V-
8-lead SOIC
8-lead SOIC
Noise vs. Frequency (Measured)
100
Dexter Research Thermopile 1M
CS3001
R2 64.9k
nV/Hz
10
R1 100
C1 0.015F
1 0.001
0.01
0.1 Frequency (Hz)
1
10
Thermopile Amplifier with a Gain of 650 V/V
Preliminary Product Information
Cirrus Logic, Inc. http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2002 (All Rights Reserved)
(c)
OCT `02 DS490PP1 1
CS3001 CS3002
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ................................................... 3 1.1 Electrical Characteristics ...................................................................................... 3 1.2 Absolute Maximum Ratings ................................................................................. 4 2. PERFORMANCE PLOTS ......................................................................................... 4 3. CS3001/CS3002 OVERVIEW ................................................................................... 7 3.1 Open Loop Gain and Phase Response .................................................................. 7 3.2 Open Loop Gain and Stability Compensation ...................................................... 8 3.3 Powerdown (PDWN) ......................................................................................... 10 3.4 Applications ........................................................................................................ 11 4. PACKAGE DRAWING ........................................................................................... 13 5. ORDERING INFORMATION ............................................................................... 14
LIST OF FIGURES
Figure 1. Noise vs Frequency (Measured) .........................................................................4 Figure 2. 0.01 Hz to 10 Hz Noise .......................................................................................4 Figure 3. Noise vs Frequency ............................................................................................4 Figure 4. Offset Voltage Stability (DC to 3.2 Hz) ...............................................................4 Figure 5. Open Loop Gain and Phase vs Frequency .........................................................5 Figure 6. Open Loop Gain and Phase vs Frequency (Expanded) .....................................5 Figure 7. Input Bias Current vs Supply Voltage (CS3002) .................................................6 Figure 8. Input Bias Current vs Common Mode Voltage ...................................................6 Figure 9. CS3001/CS3002 Open Loop Gain and Phase Response ..................................7 Figure 10. Non-Inverting Gain Configuration .....................................................................8 Figure 11. Non-Inverting Gain Configuration with Compensation ......................................9 Figure 12. Loop Gain Plot: Unity Gain and with Pole-Zero Compensation ......................10 Figure 13. Thermopile Amplifier with a Gain of 650 V/V ..................................................11 Figure 14. Load Cell Bridge Amplifier and A/D Converter ...............................................12
Contacting Cirrus Logic Support
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IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
2
CS3001 CS3002
1. CHARACTERISTICS AND SPECIFICATIONS
1.1 Electrical Characteristics
CS3001/CS3002 Parameter Input Offset Voltage Average Input Offset Drift Long Term Input Offset Voltage Stability Input Bias Current Input Offset Current Input Noise Voltage Density RS = 100 , f0 = 1 Hz RS = 100 , f0 = 1 kHz Input Noise Voltage Input Noise Current 0.1 to 10 Hz 0.1 to 10 Hz * (Note 4) (Note 5) * * * * Input Noise Current Density f0 = 1 Hz Input Common Mode Voltage Range Common Mode Rejection Ratio (dc) Power Supply Rejection Ratio Large Signal Voltage Gain RL = 2 k to V+/2 Output Voltage Swing RL = 2 k to V+/2 RL = 100 k to V+/2 Slew Rate Overload Recovery Time Supply Current per Amplifier PWDN active (CS3001 Only) PWDN Threshold Start-up Time (Note 6) (Note 6) (Note 7) * * * * RL = 2 k, 100 pF (V+) -1.0 TA = 25 C * TA = 25 C * -0.1 115 120 200 +4.7 6 6 125 2 40 120 136 300 +4.99 5 100 1.8 9 (V+)-1.25 2.4 15 12 200 (Note 2) (Note 2) * * Min Typ 0.01 (Note 3) 100 200 1000 400 2000 pA pA pA pA
nV/ Hz nV/ Hz
V+ = +5 V, V- = 0V, VCM = 2.5 V (Note 1)
Max 10 0.05
Unit V V/C
nVp-p
pA/ Hz
pAp-p V dB dB dB V V V/s s mA A V ms
Notes: 1. Symbol "*" denotes specification applies over -40 to +85 C. 2. This parameter is guaranteed by design and laboratory characterization. Thermocouple effects prohibit accurate measurement of these parameters in automatic test systems. 3. 1000-hour life test data @ 125 C indicates randomly distributed variation approximately equal to measurement repeatability of 1 V. 4. Measured within the specified common mode range limits. 5. Guaranteed within the output limits of (V+ -0.3 V) to (V- +0.3 V). Tested with proprietary production test method. 6. PWDN input has an internal pullup resistor to V+ of approximately 800 k and is the major source of current consumption when PWDN is active low. 7. The device has a controlled start-up behavior due to its complex open loop gain characteristics. Startup time applies when supply voltage is applied or when PDWN is released.
3
CS3001 CS3002
1.2 Absolute Maximum Ratings
Parameter Supply Voltage Input Voltage Storage Temperature Range [(V+) - (V-)] V- -0.3 -65 Min Typ Max 6.8 V+ +0.3 +150 Unit V V C
2. PERFORMANCE PLOTS
Noise vs. Frequency (Measured)
100
nV/Hz
1000
100
nV/Hz
10
10
1 0.001
1 10
0.01 0.1 Frequency (Hz) 1 10
100
1K
10K
100K
1M
10M
Frequency (Hz)
Figure 1. Noise vs Frequency (Measured)
Figure 3. Noise vs Frequency
100 50
100 75 50 25 0 -25 -50 -75 -100 Time (1 Hour) nV
= 13 nV
nV
0 -50
-100
0
1
2
3
4
5
6
7
8
9
10
TIME (Sec)
Figure 2. 0.01 Hz to 10 Hz Noise
Figure 4. Offset Voltage Stability (DC to 3.2 Hz)
4
CS3001 CS3002
Performance Plots (Cont.)
500 400 300 200 100 0 -100 -200 -300 -400 -500 1 10 100 1K
Gain (dB) Phase (Degrees)
Gain
Phase
10K
100K
1M
10M
Frequency (Hz)
Figure 5. Open Loop Gain and Phase vs Frequency
100
80
Gain (dB) Phase (Degrees)
60
40
20
0 -45 -90 -135 -180 -225 -270 -315 -360 10K 100K 1M 10M
Figure 6. Open Loop Gain and Phase vs Frequency (Expanded)
5
CS3001 CS3002
Performance Plots (Cont.)
-150
Input Bias Current (pA)
-100 -50 0 -50 -100 -150 -200 1.35 CM = 0 V 2 2.5
A1A1+ B1A2+ B1+ A2-
B2B2+ 3.35
Supply Voltage (V)
Figure 7. Input Bias Current vs Supply Voltage (CS3002)
Bias Current Normalized to CM = 2.5 V
3 2 1 0 -1 -2 -3 0 1 2 3 4 5 Common Mode Voltage (Vs = 5V)
Figure 8. Input Bias Current vs Common Mode Voltage
6
CS3001 CS3002
3. CS3001/CS3002 OVERVIEW
The CS3001/CS3002 amplifiers are designed for precision measurement of signals from DC to 2 kHz when operating from a supply voltage of +2.7 V to +6.7 V ( 1.35 to 3.35 V). The amplifiers are designed with a patented architecture that utilizes multiple amplifier stages to yield very high open loop gain at frequencies of 10 kHz and below. The amplifiers yield low noise and low offset drift while consuming relatively low supply current. An increase in noise floor above 2 kHz is the result of intermediate stages of the amplifier being operated at very low currents. The amplifiers are intended for amplifying small signals with large gains in applications where the output of the amplifier can be band-limited to frequencies below 2 kHz. 3.1 Open Loop Gain and Phase Response Figure 9 illustrates the open loop gain and phase response of the CS3001/CS3002. The gain slope of the amplifier is about -100 dB/decade between 500 Hz and 60 kHz and transitions to -20 dB/decade between 60 kHz and its unity gain crossover frequency at about 4.8 MHz. Phase margin at unity gain is about 70 degrees; gain margin is about 20 dB.
100
80
-100 dB/ dec
Gain (dB)
60
40
-20 dB/ dec
20
0 -45
Phase (Degrees)
-90 -135 -180 -225 -270 -315 -360 10K 100K 1M 10M
Figure 9. CS3001/CS3002 Open Loop Gain and Phase Response
7
CS3001 CS3002
Open Loop Gain and Stability Compensation The CS3001 and CS3002 achieve ultra-high open loop gain. Figure 10 illustrates the amplifier in a non-inverting gain configuration. The open loop gain and phase plots indicate that the amplifier is stable for closed-loop gains less than 50 V/V. For a gain of 50, the phase margin is between 40 and 60 depending upon the loading conditions. As shown in Figure 11 on page 9, the op amp has an input capacitance at the + and - signal inputs of typically 3.2 50 pF. This capacitance adds an additional pole in the loop gain transfer function at a frequency of f = 1/(2R*Cin) where R is the parallel combination of R1 and R2 (R1 || R2). A higher value for R produces a pole at a lower frequency, thus reducing the phase margin. R1 is recommended to be less than or equal to 100 ohms, which results in a pole at 30 MHz or higher. If a higher value of R1 is desired, a compensation capacitor (C2) should be added in parallel with R2. C2 should be chosen such that R2*C2 R1*Cin.
RS V in
Vo
R2
R1
Figure 10. Non-Inverting Gain Configuration
8
CS3001 CS3002
V in C in 50 p F Vo
50 p F C in
R2
C2
Figure 11. Non-Inverting Gain Configuration with Compensation
The feedback capacitor C2 is required for closedloop gains greater than 50 V/V. The capacitor introduces a pole and a zero in the loop gain transfer function,
s - 1 + ---z1 T = ---------------------- A ol s 1 + ---p1

This indicates that the separation of the pole and the zero is governed by the closed loop gain. It is required that the zero falls on the steep slope (-100 dB/decade) of the loop gain plot so that there is some gain higher than 0 dB (typically 20 dB) at the hand-over frequency (the frequency at which the slope changes from - 100 dB/decade to -20 dB/decade).
1 1 P 1 = ------------------------------------ -----------------------2 ( R 1 || R 2 )C 2 2 ( R 1 C 2 )
for
R2 R1
1 Z 1 = ----------------------------------2 ( A x R 1 )C 2
where
R2 A = ----R1
R1
C h o o se C 2 so th at R 2C 2
R 1C in
9
CS3001 CS3002
The loop gain plot shown in Figure 12 illustrates the unity gain configuration, and indicates how this is modified when using the amplifier in a higher gain configuration with compensation. If it is configured for higher gain, for example, 60 dB, the x-axis will move up by 60 dB (line B). Capacitor C2 adds a zero and a pole. The modified plot indicates the effects of introducing the pole and zero due to capacitor C2. The pole can be located at any frequency higher than the hand-over frequency, the zero has to be at a frequency lower than the handover frequency so as to provide adequate gain margin. The separation between the pole and the zero is governed by the closed loop gain. The zero (z1) occurs at the intersection of the -100 dB/decade and -80 dB/decade slopes. The point X in the figure should be at closed loop gain plus 20 dB gain margin. The value for C2 = 1/(2R1p1). Using p1 = 1 MHz works very well and is independent of gain. As the closed loop gain is changed, the zero location is also modified if R1 remains fixed. Capacitor C2 can be increased in value to limit the amplifier's rising noise above 2 kHz. 3.3 Powerdown (PDWN) The CS3001 single amplifier provides a powerdown function on pin 1. If this pin is left open the amplifier will operate normally. If the powerdown is asserted low, the amplifier will go into a low power state. There is a pull-up resistor (approximately 800 k ohm) inside the amplifier from pin 1 to the V+ supply. The current through this pull-up resistor is the main source of current drain in the powerdown state. 3.4 Applications The CS3001 and CS3002 amplifiers are optimum for applications that require high gain and low drift. Figure 13 illustrates a thermopile amplifier with a gain of 650 V/V. The thermopile outputs only a few millivolts when subjected to infrared radiation. The amplifier is compensated and bandlimited by C1 in combination with R2.
-100 dB/dec
|T| (Log gain)
z1 p1
-80 dB/dec
X
Margin B
-20 dB/dec
50kHz 1MHz
Desired Closed Loop Gain
5MHz
FREQUENCY
Figure 12. Loop Gain Plot: Unity Gain and with Pole-Zero Compensation
10
CS3001 CS3002
Figure 14 on page 12 illustrates a load cell bridge amplifier with a gain of 768 V/V. The load cell is excited with +5 V and has a 1 mV/V sensitivity. Its full scale output signal is amplified to produce a fully differential 3.8 V into the CS5510/12 A/D converter. This circuit operates from +5 V. A similar circuit operating from +3 V can be constructed using the CS5540/CS5541 A/D converters.
C S 3 00 1
D exter Research Therm opile 1M
R2 6 4 .9k
R1 10 0
C1 0 .0 1 5 F
T h e rm o p ile A m p lifie r w ith a G ain o f 65 0 V /V
Figure 13. Thermopile Amplifier with a Gain of 650 V/V
11
CS3001 CS3002
+5 V VA
+5 V 0 .1 F V+ x768 VREF 1 00 A IN + 1 4 0 k 0 .2 2 F CS SDO SC LK C S 5 5 1 0 /1 2
+5 V
+
1 m V /V -
350
+ 365 0 .0 4 7 F
+
1 4 0 k
0 .2 2 F A IN 1 100 V-
C o u n te r /T im e r
S C L K = 1 0 k H z to 1 0 0 k H (3 2 .7 6 8 l) S C L K = 1 0 ik H z t o 1 0 0 k H z ( 3 2 . 7 6 8 n o m i n a l)
Figure 14. Load Cell Bridge Amplifier and A/D Converter
12
CS3001 CS3002
4. PACKAGE DRAWING 8L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1 b c
D SEATING PLANE e A1
A L
INCHES DIM A A1 B C D E e H L MIN 0.053 0.004 0.013 0.007 0.189 0.150 0.040 0.228 0.016 0 MAX 0.069 0.010 0.020 0.010 0.197 0.157 0.060 0.244 0.050 8 JEDEC # : MS-012
MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.02 1.52 5.80 6.20 0.40 1.27 0 8
13
CS3001 CS3002
5. ORDERING INFORMATION
Part # CS3001-IS CS3002-IS Temperature Range -40 C to +85 C -40 C to +85 C Package Description 8-lead SOIC 8-lead SOIC
Note: Add the letter R to the Part # to order reels. There are 2000 pieces per reel.
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* Notes *

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